It is known that for producing monocrystalline semiconductor films, there are various methods and processes, which are often complex and expensive. Although it is relatively easy to produce polycrystalline or amorphous material films, it is much more difficult to produce monocrystalline films. Among the methods used for producing monocrystalline films are those used for producing silicon on insulator (SOI) substrates, where the aim is to produce a monocrystalline silicon film on a substrate that is electrically insulated from the film.
A conventional SOI wafer cross section is shown in FIG. 1. An insulating layer 15 is formed on a substrate 10. A device layer 20 is formed on the insulating layer 15. SOI wafers are known in microelectronics and are used in special applications, including radiation hardened devices such as static random access memories (SRAMs), and more recently for high performance complementary metal oxide semiconductor (CMOS) and dynamic random access memory (DRAM) applications. SOI wafers are usually manufactured by 1) implanted oxygen (SIMOX) in which oxygen is implanted into silicon and converted into a silicon dioxide (SiO.sub.2) buried layer, or 2) wafer bonding and etch-back (BESOI) in which two wafers are bonded with oxide surface layers and one wafer is thinned to leave a thin device layer. For the past few years there has been a growing interest in SOI material technology based on BESOI. In prior art BESOI processes, multi-etch layers have been used to minimize the uniformity and tolerance problems.
Another recent process for producing SOI substrates is the Smart-Cut.RTM. process. The Smart-Cut process is described in U.S. Pat. No. 5,374,564, which is hereby incorporated by reference for its teachings on Smart-Cut. It is similar to the BESOI process, but instead of thinning by etching, it uses a hydrogen layer that is implanted prior to bonding, and the bulk silicon is fractured after bonding to leave behind a thin layer. In other words, in the Smart-Cut process, hydrogen implantation and annealing are used to fracture the bulk of the device wafer from the bonded wafers. Chemical-mechanical polishing (CMP) is used to planarize and minimize non-uniformity of the as-cut SOI wafer.
The Smart-Cut process has the following steps: 1) a device wafer is processed to have a device quality surface layer, an oxide layer is provided over the device layer, and a buried hydrogen-rich layer is implanted at a certain depth; 2) a "handle wafer" with an oxide surface is provided; 3) the device wafer is flipped and the oxide surfaces are bonded; 4) the structure is annealed to form connecting voids from hydride formation; 5) the structure is fractured; and 6) the transferred device layer is CMP polished and cleaned.
FIG. 2 is a flow diagram of the process steps for forming an SOI substrate using the Smart-Cut process. FIGS. 3A to 3C are diagrams that illustrate the steps in FIG. 2. A device quality wafer 200 is provided at step 100. The wafer surface is oxidized at step 105 so that it is capped or buffered with a thermally grown SiO.sub.2 layer 205 (i.e., a dielectric layer). The dielectric layer 205 becomes the buried oxide of the SOI structure. Hydrogen ions are implanted at 50 to 150 KeV at step 110 with a dosage of 2.times.10.sup.16 to 1.times.10.sup.17 ions/cm.sup.2 to form a hydrogen-rich layer 210 about 0.5 to 1 .mu.m below the top surface, as shown in FIG. 3A. The thin silicon layer that will be the device layer is shown as layer 207.
The device wafer 200 and a supporting substrate (a nonimplanted handle wafer) 220 are cleaned in step 115 using conventional cleaning techniques such as the RCA wafer cleaning procedure. The surfaces of the device wafer 200 and the supporting substrate 220 are made hydrophilic and are bonded together at room temperature in step 120, as shown in FIG. 3B. The supporting substrate 220 acts as a stiffener and provides the bulk silicon under the buried oxide in the SOI structure.
In hydrophilic (or "direct") bonding, a hydroxyl group (OH.sup.-) is formed on a material surface due to the presence of an electric charge of atoms. Furthermore, several layers of water molecules are formed around hydroxyl groups on the surface. When such two ionic materials each having a sufficiently flat face are attached to each other, they are firmly bonded together through hydrophilic bonding by the hydrogen bond formed among the hydroxyl groups and water molecules. Thus, the flat faces of the ionic materials can be hydrophilic bonded with each other without using adhesives. A subsequent annealing makes the bonding stronger.
A two-phase heat treatment is applied to the two bonded wafers 200 and 220. In step 125, the bonded wafers 200 and 220 are annealed to about 400.degree. to 600.degree. C., which promotes the formation and linkage of regions of brittle silicon hydride. When the hydride regions are completely linked across the wafer, the device wafer 200 is fractured and separated from the bonded stack along the hydride rich plane. The thin silicon layer 207 remains bonded to the support substrate 220, as shown in FIG. 3C. Then, the support substrate 220 with the thin silicon layer 207 (device layer) still bonded to it is annealed at a high temperature (approximately 1000.degree. C.) to promote a stronger bonding between the support substrate 220 and the device layer 207. After splitting, the separated surface of the device usually has a roughness on the order of a few hundred angstroms. A CMP is carried out at step 130 to reduce the roughness of the surface. Thus, despite good control of the thickness allowed by the implantation process, the final thickness uniformity and surface roughness are mainly dependent on the CMP parameters.
One disadvantage of the Smart-Cut process is that the roughness of the as-cut surface requires polishing (e.g., CMP) to smooth the surface. This polishing affects the thickness uniformity of the device layer across the wafer. Thus, the polishing process, while improving roughness, simultaneously creates thickness variation.
Another disadvantage is that it is not easy to obtain very thin device layers (on the order of about 3.9.times.10.sup.-6 inch (1000 .ANG.) thick) using the Smart-Cut process because the hydrogen implant and spreading will have a large uncertainty, which necessitates beginning with the formation of a thicker layer and thinning it down to control within a tolerance of a couple of hundred angstroms. However, the roughness of the as-split wafer in the Smart-Cut process is typically in the range of about 3.9.times.10.sup.-7 to 7.8.times.10.sup.-7 inch (100 to 200 .ANG.). Thus, the Smart-Cut process is not well suited for these thin layer devices.
Other methods of fabricating SOI structures use etch stop or etch selective layers, For example, in some versions of BESOI processing, etch stop layers are used in conjunction with CMP to improve thickness and uniformity control. In the prior art processes, however, etching and etch stop layers are used in addition to CMP,
Although the art of producing monocrystalline films is well developed, there remain some problems inherent in this technology, One particular problem is that the final thickness of the device layer and the uniformity are not easily controlled due to polishing to remove surface roughness. Therefore, a need exists for a process that is similar to the Smart-Cut process, but does not suffer from thickness variations due to a polishing operation. There is also a need for a process that is compatible with silicon manufacturing, where uniformity and thickness of the SOI device layer can be selected and controlled independent of the Smart-Cut process.